A modern storage device may be viewed as a single entity from the perspective of system or application level software, for example, but the storage device may actually comprise a number of different physical memory storage units or devices, such as physical dynamic random access memory (DRAM) devices. From the perspective of system or application software, the address space of a memory with a plurality of physical memory storage devices may appear to be a continuous logical address space. Consequently, system or application software may employ logical addresses (LAs) to access memory, but an LA may need to be mapped to a physical address (PA) in order to retrieve data from memory. Part of this mapping may involve determining the identity of the physical memory storage device (from among a plurality of storage devices) containing the data to be retrieved. In some memory architectures, once the physical memory storage device is identified, the LA may be transmitted to that storage device, where a final step of determining the PA may be performed and data retrieved from a memory location corresponding to the PA. Converting an LA into an identifier of a physical memory device and a PA of the physical memory device may be referred to as memory translation. The details of memory translation may be hidden from other parts of the system connected to the memory device and performed in the memory device itself or in related hardware or software.
A mapping of an LA to a PA may be performed in one clock cycle and with simple operations if the number of physical memory storage units or devices is a power of two. For example, if the logical address space spans n physical memory storage units, where n is a power of two, identifying the particular physical memory unit corresponding to a particular LA may involve shifting log2 n bits out of the LA to identify the physical memory unit. Such operations may be all that is needed to implement a modulo n operation. Further determining the PA given the identity of the memory unit may also be relatively simple if the number of memory units is a power of two.
In some scenarios it may be desirable for the number of physical memory storage devices in a memory to be an arbitrary number that is not restricted to be a power of two. For example, in a memory in which speed, cost, chip area, and/or power may be at a premium, configuring a memory using five physical memory storage devices, such as five DRAM chips, rather than eight physical memory storage devices may be preferable. However, in such situations, mapping an LA to a PA may become more complex. A modulo operation to identify the physical memory storage device corresponding to data to be retrieved may involve costly and/or slow division circuits to perform the mapping. For example, supposing an LA is represented by K bits, where K is an arbitrary integer, a modulo n operation to identify the physical memory storage device corresponding to the LA may involve a division operation using all K bits of the LA, if conventional or brute-force techniques are employed. The larger the value of K, the more costly the division operation in terms of memory access speed and/or cost. These issues may be particularly acute if the memory employs striped and non-striped regions. There is thus a need to reduce complexity and/or increase speed of a translation of LAs to PAs in memory devices with an arbitrary number of physical memory units.